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NVIDIA NCP-AII Practice Test 114

Question 1130

During an NVIDIA AI factory acceptance test, engineers discover: A GPU server with AMD EPYC CPUs feeds remote socket memory to local accelerators and preprocessing throughput falls. Which TWO complementary elements are needed: the correct technical action and the strongest independent diagnostic evidence? Select TWO answers.

  1. Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing.
  2. Review kernel and NVIDIA Xid logs, driver version, concurrent workload, ECC state and vendor diagnostic guidance.
  3. Measure locality and CPU-memory traffic, then use approved AMD platform NUMA and affinity settings for the workload.
  4. Evaluate protected storage layout, rebuild behavior, workload concurrency and sustained dataset throughput.
  5. Inspect lscpu NUMA topology, numactl placement, memory bandwidth, CPU affinity and GPU data-feed stalls.

Explanation

Correct Answers

C:

This is an appropriate correction for AMD host CPU NUMA and memory tuning: Measure locality and CPU-memory traffic, then use approved AMD platform NUMA and affinity settings for the workload. Observed scenario: A GPU server with AMD EPYC CPUs feeds remote socket memory to local accelerators and preprocessing throughput falls. The governing mechanism is: Multi-socket host data movement can limit accelerator utilization even when GPU kernels themselves are efficient.

E:

This is the direct operational evidence to investigate: Inspect lscpu NUMA topology, numactl placement, memory bandwidth, CPU affinity and GPU data-feed stalls. Observed scenario: A GPU server with AMD EPYC CPUs feeds remote socket memory to local accelerators and preprocessing throughput falls.

Incorrect Answers

A:

This tempting but unsafe shortcut is not a sufficient remediation for AMD host CPU NUMA and memory tuning: Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing. Multi-socket host data movement can limit accelerator utilization even when GPU kernels themselves are efficient.

B:

This alternative is relevant to NVIDIA GPU Xid event root cause isolation but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: Review kernel and NVIDIA Xid logs, driver version, concurrent workload, ECC state and vendor diagnostic guidance. Observed scenario: A GPU server with AMD EPYC CPUs feeds remote socket memory to local accelerators and preprocessing throughput falls.

D:

This alternative is relevant to Storage array throughput and RAID or erasure recovery but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: Evaluate protected storage layout, rebuild behavior, workload concurrency and sustained dataset throughput. Observed scenario: A GPU server with AMD EPYC CPUs feeds remote socket memory to local accelerators and preprocessing throughput falls.

Question 1131

A production GPU cluster review identifies this condition: A GPU server with AMD EPYC CPUs feeds remote socket memory to local accelerators and preprocessing throughput falls. Which diagnostic evidence should be obtained FIRST to substantiate the likely fault or configuration gap? Select ONE best answer.

  1. Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing.
  2. Inspect array fault state, protection topology, rebuild progress, queue depth, and read-write benchmark trends.
  3. Inspect lscpu NUMA topology, numactl placement, memory bandwidth, CPU affinity and GPU data-feed stalls.
  4. Inspect nvidia-smi ECC history, DCGM alerts, remapped rows, Xid logs and stress test results.

Explanation

Correct Answer

C:

This is the direct operational evidence to investigate: Inspect lscpu NUMA topology, numactl placement, memory bandwidth, CPU affinity and GPU data-feed stalls. Observed scenario: A GPU server with AMD EPYC CPUs feeds remote socket memory to local accelerators and preprocessing throughput falls. The governing mechanism is: Multi-socket host data movement can limit accelerator utilization even when GPU kernels themselves are efficient.

Incorrect Answers

A:

This tempting but unsafe shortcut is not a sufficient remediation for AMD host CPU NUMA and memory tuning: Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing. A GPU server with AMD EPYC CPUs feeds remote socket memory to local accelerators and preprocessing throughput falls.

B:

This alternative is relevant to Storage array throughput and RAID or erasure recovery but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: Inspect array fault state, protection topology, rebuild progress, queue depth, and read-write benchmark trends. Observed scenario: A GPU server with AMD EPYC CPUs feeds remote socket memory to local accelerators and preprocessing throughput falls.

D:

This alternative is relevant to GPU ECC and memory reliability diagnosis but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: Inspect nvidia-smi ECC history, DCGM alerts, remapped rows, Xid logs and stress test results. Observed scenario: A GPU server with AMD EPYC CPUs feeds remote socket memory to local accelerators and preprocessing throughput falls.

Question 1132

In a professional AI infrastructure deployment, a technician observes: A GPU server with AMD EPYC CPUs feeds remote socket memory to local accelerators and preprocessing throughput falls. After corrective work, which observable result BEST confirms that the requirement is met? Select ONE best answer.

  1. The repaired node sustains approved clocks and performance with normal fan state under representative load.
  2. The identified cause is addressed and repeated representative work runs without the original Xid failure.
  3. Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing.
  4. Representative data-loading and training workloads improve within tested stable NUMA and CPU binding policy.

Explanation

Correct Answer

D:

This is an observable verified result, not merely a claimed configuration change: Representative data-loading and training workloads improve within tested stable NUMA and CPU binding policy. Observed scenario: A GPU server with AMD EPYC CPUs feeds remote socket memory to local accelerators and preprocessing throughput falls.

Incorrect Answers

A:

This alternative is relevant to Fan faults and thermal throttling investigation but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: The repaired node sustains approved clocks and performance with normal fan state under representative load. Observed scenario: A GPU server with AMD EPYC CPUs feeds remote socket memory to local accelerators and preprocessing throughput falls.

B:

This alternative is relevant to NVIDIA GPU Xid event root cause isolation but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: The identified cause is addressed and repeated representative work runs without the original Xid failure. Observed scenario: A GPU server with AMD EPYC CPUs feeds remote socket memory to local accelerators and preprocessing throughput falls.

C:

This tempting but unsafe shortcut is not a sufficient remediation for AMD host CPU NUMA and memory tuning: Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing. A GPU server with AMD EPYC CPUs feeds remote socket memory to local accelerators and preprocessing throughput falls. Multi-socket host data movement can limit accelerator utilization even when GPU kernels themselves are efficient.

Question 1133

The cluster operations team needs to evaluate this situation: An AMD BIOS change alters NUMA node presentation while scheduling CPU affinities remain unchanged. Which operational response is MOST appropriate to address the root issue? Select ONE best answer.

  1. Correlate cooling airflow, fan health, ambient inlet and clock-throttle reasons; repair root cause safely.
  2. Measure locality and CPU-memory traffic, then use approved AMD platform NUMA and affinity settings for the workload.
  3. Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing.
  4. Localize HCA, port, optic, cabling and PCIe causes before replacing the approved failed component.

Explanation

Correct Answer

B:

This is an appropriate correction for AMD host CPU NUMA and memory tuning: Measure locality and CPU-memory traffic, then use approved AMD platform NUMA and affinity settings for the workload. Observed scenario: An AMD BIOS change alters NUMA node presentation while scheduling CPU affinities remain unchanged.

Incorrect Answers

A:

This alternative is relevant to Fan faults and thermal throttling investigation but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: Correlate cooling airflow, fan health, ambient inlet and clock-throttle reasons; repair root cause safely. Observed scenario: An AMD BIOS change alters NUMA node presentation while scheduling CPU affinities remain unchanged.

C:

This tempting but unsafe shortcut is not a sufficient remediation for AMD host CPU NUMA and memory tuning: Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing. An AMD BIOS change alters NUMA node presentation while scheduling CPU affinities remain unchanged.

D:

This alternative is relevant to Failed ConnectX HCA or port fault isolation but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: Localize HCA, port, optic, cabling and PCIe causes before replacing the approved failed component. Observed scenario: An AMD BIOS change alters NUMA node presentation while scheduling CPU affinities remain unchanged.

Question 1134

At a multi-node AI infrastructure handoff, the team records: An AMD BIOS change alters NUMA node presentation while scheduling CPU affinities remain unchanged. Which underlying infrastructure principle BEST explains the issue? Select ONE best answer.

  1. A high-speed fabric fault may originate in cable, transceiver, adapter, driver or host slot rather than the GPU.
  2. Server CPU socket topology, PCIe lane allocation and memory access shape the efficiency of host-to-GPU transfers.
  3. Multi-socket host data movement can limit accelerator utilization even when GPU kernels themselves are efficient.
  4. Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing.

Explanation

Correct Answer

C:

This is the governing infrastructure principle: Multi-socket host data movement can limit accelerator utilization even when GPU kernels themselves are efficient. Observed scenario: An AMD BIOS change alters NUMA node presentation while scheduling CPU affinities remain unchanged.

Incorrect Answers

A:

This alternative is relevant to Failed ConnectX HCA or port fault isolation but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: A high-speed fabric fault may originate in cable, transceiver, adapter, driver or host slot rather than the GPU. Observed scenario: An AMD BIOS change alters NUMA node presentation while scheduling CPU affinities remain unchanged.

B:

This alternative is relevant to Intel host CPU PCIe placement and BIOS efficiency but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: Server CPU socket topology, PCIe lane allocation and memory access shape the efficiency of host-to-GPU transfers. Observed scenario: An AMD BIOS change alters NUMA node presentation while scheduling CPU affinities remain unchanged.

D:

This tempting but unsafe shortcut is not a sufficient remediation for AMD host CPU NUMA and memory tuning: Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing. An AMD BIOS change alters NUMA node presentation while scheduling CPU affinities remain unchanged. Multi-socket host data movement can limit accelerator utilization even when GPU kernels themselves are efficient.

Question 1135

During an NVIDIA AI factory acceptance test, engineers discover: An AMD BIOS change alters NUMA node presentation while scheduling CPU affinities remain unchanged. Which diagnostic evidence should be obtained FIRST to substantiate the likely fault or configuration gap? Select ONE best answer.

  1. Inspect lscpu NUMA topology, numactl placement, memory bandwidth, CPU affinity and GPU data-feed stalls.
  2. Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing.
  3. Inspect array fault state, protection topology, rebuild progress, queue depth, and read-write benchmark trends.
  4. Compare bidirectional port counters, cable swaps, PCIe link state, adapter logs and test transfers.

Explanation

Correct Answer

A:

This is the direct operational evidence to investigate: Inspect lscpu NUMA topology, numactl placement, memory bandwidth, CPU affinity and GPU data-feed stalls. Observed scenario: An AMD BIOS change alters NUMA node presentation while scheduling CPU affinities remain unchanged.

Incorrect Answers

B:

This tempting but unsafe shortcut is not a sufficient remediation for AMD host CPU NUMA and memory tuning: Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing. Observed scenario: An AMD BIOS change alters NUMA node presentation while scheduling CPU affinities remain unchanged. The governing mechanism is: Multi-socket host data movement can limit accelerator utilization even when GPU kernels themselves are efficient. The proportionate action is: Measure locality and CPU-memory traffic, then use approved AMD platform NUMA and affinity settings for the workload.

C:

This alternative is relevant to Storage array throughput and RAID or erasure recovery but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: Inspect array fault state, protection topology, rebuild progress, queue depth, and read-write benchmark trends. Observed scenario: An AMD BIOS change alters NUMA node presentation while scheduling CPU affinities remain unchanged.

D:

This alternative is relevant to Failed ConnectX HCA or port fault isolation but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: Compare bidirectional port counters, cable swaps, PCIe link state, adapter logs and test transfers. Observed scenario: An AMD BIOS change alters NUMA node presentation while scheduling CPU affinities remain unchanged.

Question 1136

A production GPU cluster review identifies this condition: An AMD BIOS change alters NUMA node presentation while scheduling CPU affinities remain unchanged. After corrective work, which observable result BEST confirms that the requirement is met? Select ONE best answer.

  1. The replacement supply operates normally and a tested approved single-feed failure preserves required service.
  2. Representative data-loading and training workloads improve within tested stable NUMA and CPU binding policy.
  3. Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing.
  4. The repaired path maintains intended negotiated performance with acceptable errors under repeated RDMA stress.

Explanation

Correct Answer

B:

This is an observable verified result, not merely a claimed configuration change: Representative data-loading and training workloads improve within tested stable NUMA and CPU binding policy. Observed scenario: An AMD BIOS change alters NUMA node presentation while scheduling CPU affinities remain unchanged.

Incorrect Answers

A:

That option concerns Redundant PSU and power path failure replacement. Multi-socket host data movement can limit accelerator utilization even when GPU kernels themselves are efficient.

C:

This tempting but unsafe shortcut is not a sufficient remediation for AMD host CPU NUMA and memory tuning: Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing. Observed scenario: An AMD BIOS change alters NUMA node presentation while scheduling CPU affinities remain unchanged. The governing mechanism is: Multi-socket host data movement can limit accelerator utilization even when GPU kernels themselves are efficient. The proportionate action is: Measure locality and CPU-memory traffic, then use approved AMD platform NUMA and affinity settings for the workload. A direct check is: Inspect lscpu NUMA topology, numactl placement, memory bandwidth, CPU affinity and GPU data-feed stalls. The acceptance condition is: Representative data-loading and training workloads improve within tested stable NUMA and CPU binding policy.

D:

This alternative is relevant to Failed ConnectX HCA or port fault isolation but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: The repaired path maintains intended negotiated performance with acceptable errors under repeated RDMA stress. Observed scenario: An AMD BIOS change alters NUMA node presentation while scheduling CPU affinities remain unchanged.

Question 1137

In a professional AI infrastructure deployment, a technician observes: A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links. Which operational response is MOST appropriate to address the root issue? Select ONE best answer.

  1. Localize HCA, port, optic, cabling and PCIe causes before replacing the approved failed component.
  2. Measure locality and CPU-memory traffic, then use approved AMD platform NUMA and affinity settings for the workload.
  3. Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing.
  4. Correlate specific Xid codes and timing with GPU, driver, application and fabric evidence before remediation.

Explanation

Correct Answer

B:

This is an appropriate correction for AMD host CPU NUMA and memory tuning: Measure locality and CPU-memory traffic, then use approved AMD platform NUMA and affinity settings for the workload. Observed scenario: A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links.

Incorrect Answers

A:

This alternative is relevant to Failed ConnectX HCA or port fault isolation but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: Localize HCA, port, optic, cabling and PCIe causes before replacing the approved failed component. Observed scenario: A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links.

C:

This tempting but unsafe shortcut is not a sufficient remediation for AMD host CPU NUMA and memory tuning: Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing. A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links.

D:

This alternative is relevant to NVIDIA GPU Xid event root cause isolation but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: Correlate specific Xid codes and timing with GPU, driver, application and fabric evidence before remediation. Observed scenario: A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links.

Question 1138

The cluster operations team needs to evaluate this situation: A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links. Which underlying infrastructure principle BEST explains the issue? Select ONE best answer.

  1. Multi-socket host data movement can limit accelerator utilization even when GPU kernels themselves are efficient.
  2. GPU memory error handling can mask or retire damaged regions; recurring serious errors require reliability assessment.
  3. A high-speed fabric fault may originate in cable, transceiver, adapter, driver or host slot rather than the GPU.
  4. Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing.

Explanation

Correct Answer

A:

This is the governing infrastructure principle: Multi-socket host data movement can limit accelerator utilization even when GPU kernels themselves are efficient. Observed scenario: A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links.

Incorrect Answers

B:

This alternative is relevant to GPU ECC and memory reliability diagnosis but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: GPU memory error handling can mask or retire damaged regions; recurring serious errors require reliability assessment. Observed scenario: A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links.

C:

This alternative is relevant to Failed ConnectX HCA or port fault isolation but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: A high-speed fabric fault may originate in cable, transceiver, adapter, driver or host slot rather than the GPU. Observed scenario: A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links.

D:

This tempting but unsafe shortcut is not a sufficient remediation for AMD host CPU NUMA and memory tuning: Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing. A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links. Multi-socket host data movement can limit accelerator utilization even when GPU kernels themselves are efficient.

Question 1139

At a multi-node AI infrastructure handoff, the team records: A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links. Which diagnostic evidence should be obtained FIRST to substantiate the likely fault or configuration gap? Select ONE best answer.

  1. Review kernel and NVIDIA Xid logs, driver version, concurrent workload, ECC state and vendor diagnostic guidance.
  2. Inspect array fault state, protection topology, rebuild progress, queue depth, and read-write benchmark trends.
  3. Inspect lscpu NUMA topology, numactl placement, memory bandwidth, CPU affinity and GPU data-feed stalls.
  4. Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing.

Explanation

Correct Answer

C:

This is the direct operational evidence to investigate: Inspect lscpu NUMA topology, numactl placement, memory bandwidth, CPU affinity and GPU data-feed stalls. Observed scenario: A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links.

Incorrect Answers

A:

This alternative is relevant to NVIDIA GPU Xid event root cause isolation but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: Review kernel and NVIDIA Xid logs, driver version, concurrent workload, ECC state and vendor diagnostic guidance. Observed scenario: A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links.

B:

This alternative is relevant to Storage array throughput and RAID or erasure recovery but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: Inspect array fault state, protection topology, rebuild progress, queue depth, and read-write benchmark trends. Observed scenario: A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links.

D:

This tempting but unsafe shortcut is not a sufficient remediation for AMD host CPU NUMA and memory tuning: Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing. Observed scenario: A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links. The governing mechanism is: Multi-socket host data movement can limit accelerator utilization even when GPU kernels themselves are efficient. The proportionate action is: Measure locality and CPU-memory traffic, then use approved AMD platform NUMA and affinity settings for the workload.

Question 1140

During an NVIDIA AI factory acceptance test, engineers discover: A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links. Which TWO complementary elements are needed: the correct technical action and the strongest independent diagnostic evidence? Select TWO answers.

  1. Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing.
  2. Inspect CPU socket and PCIe mapping, negotiated lane width, NUMA bindings, BIOS changes and measured throughput.
  3. Inspect lscpu NUMA topology, numactl placement, memory bandwidth, CPU affinity and GPU data-feed stalls.
  4. Measure locality and CPU-memory traffic, then use approved AMD platform NUMA and affinity settings for the workload.
  5. Evaluate protected storage layout, rebuild behavior, workload concurrency and sustained dataset throughput.

Explanation

Correct Answers

C:

This is the direct operational evidence to investigate: Inspect lscpu NUMA topology, numactl placement, memory bandwidth, CPU affinity and GPU data-feed stalls. Observed scenario: A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links. The governing mechanism is: Multi-socket host data movement can limit accelerator utilization even when GPU kernels themselves are efficient.

D:

This is an appropriate correction for AMD host CPU NUMA and memory tuning: Measure locality and CPU-memory traffic, then use approved AMD platform NUMA and affinity settings for the workload. Observed scenario: A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links. The governing mechanism is: Multi-socket host data movement can limit accelerator utilization even when GPU kernels themselves are efficient.

Incorrect Answers

A:

This tempting but unsafe shortcut is not a sufficient remediation for AMD host CPU NUMA and memory tuning: Treat all CPU cores and DRAM channels as equal-latency to every GPU because the system uses accelerated computing. Observed scenario: A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links. The governing mechanism is: Multi-socket host data movement can limit accelerator utilization even when GPU kernels themselves are efficient. The proportionate action is: Measure locality and CPU-memory traffic, then use approved AMD platform NUMA and affinity settings for the workload. A direct check is: Inspect lscpu NUMA topology, numactl placement, memory bandwidth, CPU affinity and GPU data-feed stalls. The acceptance condition is: Representative data-loading and training workloads improve within tested stable NUMA and CPU binding policy.

B:

This alternative is relevant to Intel host CPU PCIe placement and BIOS efficiency but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: Inspect CPU socket and PCIe mapping, negotiated lane width, NUMA bindings, BIOS changes and measured throughput. Observed scenario: A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links.

E:

This alternative is relevant to Storage array throughput and RAID or erasure recovery but does not directly resolve the current AMD host CPU NUMA and memory tuning issue: Evaluate protected storage layout, rebuild behavior, workload concurrency and sustained dataset throughput. Observed scenario: A training job suffers CPU bottlenecks despite idle GPU memory bandwidth and acceptable fabric links.

NCP-AI Infrastructure (NCP-AII) Practice Tests